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IspLEVER Classic Software ispLEVER Classic is the design environment for Lattice CPLDs and mature programmable products. It can be used to take a Lattice device design completely through the design process, from concept to device JEDEC or Bitstream programming file output. The ispLEVER software follows an im plementation flow that generates a programming file from your CPLD design files. A similar flow exists within the Quartus II software known as the compilation flow. The compilation flow is the sequence and method by which the Quartus II.
Basic Information
- SDU Course Number: SD01331470, SD01331480
- Instructor(s): Assistant Prof Feng Li (李峰, fli@sdu.edu.cn)
- Terms offered: Fall 2016
- Level: Undergraduate
- Teaching Assistant(s): Ms Zhenjuan Qiao (乔贞娟, 1847086166@qq.com), Mr Pengfei Wang (王鹏飞, 8144756@qq.com)
Course Description
This course is to introduce the basic organization and design principles of computers. The topics include computer instructions, arithmetics, processor design, storage hierarchy, etc. Through taking this course, students will understand how a computer works and how to design a computer, from the perspectives of both hardware and software.
This course consists of two parts: lectures (SD01331470) and project design (SD01331470). The grades for SD01331470 will be based on the students' performance on assignments (20%), and final exam (80%), while the ones for SD01331470 will be given according to demos and experiment reports delivered by the students.
Remarks: This website is in construction. Related materials will be uploaded as soon as possible. If you have any problem about this website, please feel free to drop me an email.
Lecture Notes
Slides for lectures
- Computer Abstractions and Technology [PDF]
- Instructions: Language of the Computer [PDF]
- Arithmetic for Computers [PDF]
- The Processor [PDF]
- Large and Fast: Exploiting Memory Hierarchy [PDF]
- Introduction [PDF]
We introduce the roadmap of our experiments. - Experiment platform [PDF]
We introduce the basic knowledge of EDA and PLD, as well as the platform of our experiments. - Introduction to Quartus [PDF]
We introduce the software platform of our experiments, Quartus. Please refer to Quartus II tutorial.
Experiments
A detailed report for each of the following experiment is required. The related materials are in Chinese. Details can be found in the experiment tutorial as well as the following slides. The template of experiment report can be downloaded by clicking here.
Lattice Isplever Tutorial
| Experiment | Due Date (Demo) | Due Date (Report) |
|---|---|---|
| Circuit for logical operations | Oct 18, 2016 | Oct 25, 2016 |
| A 4-bit Adder based on two's complement | Oct 27, 2016 | Nov 3, 2016 |
| Shifter | Nov 1, 2016 | Nov 8, 2016 |
| 8-bit ALU | Nov 4, 2016 | Nov 11, 2016 |
| 4-bit ALU based on two's complement | Nov 10, 2016 | Nov 17, 2016 |
| Microprogram control unit | Nov 18, 2016 | Nov 25, 2016 |
| A prototype of CPU | Nov 24, 2016 | Dec 1, 2016 |
| A demo of prototypical computers | Dec 1, 2016 | Dec 8, 2016 |
| Project Design: A prototypical computer | Dec 15, 2016 | Dec 29, 2016 |
Isplever Project Navigator Tutorial
Assignments
Students are supposed to submit their solutions before the due date.
- Assignment 1 [PDF] [Due Date: Sep 18, 2016]
- Assignment 2 [PDF] [Due Date: Oct 10, 2016]
- Assignment 3 [PDF] [Due Date: Nov 7, 2016]
Tutorials
Isplever Classic Tutorial
- ispLEVER tutorial i (released by Latticesemi) [PDF]
- ispLEVER tutorial ii (for designing an adder) [PDF]
- Quartus II tutorial [PDF]
Useful Links
Isplever Tutorial
- Adder on Wiki: link
- Interesting comments: link
- CD resources of the textbook: link
- PDF version of the textbook: link
- To be added...